1. Field of the Invention
The invention relates generally to the fabrication of metal layers for semiconductor devices and more particularly to the deposition of metal layers that overcome asymmetric metal deposition problems.
2. Background of the Invention
Metal layers and interconnects are important technologies in semiconductor manufacturing. Interconnects electrically connect different conductor wiring layers in a semiconductor chip. The conductive layers can be layers formed on a substrate surface or over metal wiring layers. It is important that these interconnects, vias, and conductive wiring layers be reliable, be as small as possible for miniaturization of the circuit, and have wide process windows for high yield.
Conventionally, metal layers are often deposited via a sputtering process known as physical vapor deposition (PVD). The term PVD denotes a deposition processes where the coating material is evaporated by various mechanisms, such as resistant heating, high energy ionized gas bombardment, or an electronic gun, under vacuum, and the vapor phase is transported to the substrate forming a coating. PVD is a line of site process in which atoms travel from a metallic source to the substrate on a generally straight path. A conventional PVD coating process normally takes place between temperatures of 100-600° C.
Unfortunately, the metal sputtering process can result in asymmetric deposition of the metal across the wafer.
The alignment and measurement target for a first metal, or metal one layer is structurally defined as the conformance of sputtered metal deposited over predefined, tungsten filled contacts. The predefined tungsten filled contacts can be refereed to as a metal layer registration key. The growth of metal, e.g., AlCu, Ti, TiN, etc., on the wafer surface is not, however, actually expected to be perpendicular. The direction of metal growth is actually expected to be a function of the position on the metal target and the emission angle between the position of the target and the wafer surface. From this, the spatial resultant of metal growth on the wafer surface is expected at both the translation and rotational component. As a result, conventional metal deposition processes show asymmetric deposition, especially at the wafer edge. This results in alignment read errors, because the registration key cannot be accurately detected. Such read errors are generally more pronounced at the edge of the wafer.
The read errors will affect the ML1 overlay shift and as device dimensions shrink the effect will become more serious.